Non-volatile memory array with simultaneous write and erase feature

ABSTRACT

A non-volatile transistor memory array, having individual cells, each individual cell having a current injector transistor and a non-volatile memory transistor. Injector current gives rise to charged particles that can be stored in the memory transistor by tunneling. When a row of the array is activated by a word line, the active row has current injectors ready to operate if program line voltages are appropriate to cause charge storage in a memory cell, while a cell in an adjacent row is erased by charge being driven from a memory transistor. A series of conductive plates are arranged in capacitive relation to the word line, with each plate having a pair of oppositely extending tangs, one allowing programming of a cell in a first row and another allowing erasing of a cell in another row.

CROSS-REFERENCE TO RELATED APPLICATION

This is a divisional of pending U.S. patent application Ser. No.10/773,059, filed Feb. 4, 2004 and entitled “NON-VOLATILE MEMORY ARRAYWITH SIMULTANEOUS WRITE AND ERASE FEATURE,” incorporated herein byreference.

TECHNICAL FIELD

The invention relates to non-volatile memory arrays and, in particular,to a non-volatile memory array adapted for a simultaneous write anderase.

BACKGROUND ART

Impact ionization has been known for several years. U.S. Pat. No.4,432,075 to B. Eitan and U.S. Pat. No. 4,821,236 to Hayashi et al.describe an EEPROM transistor adjacent to a charge generator, creating asubstrate current near the EEPROM, creating excess charge or holes,resembling space charge, near subsurface electrodes of the EEPROM.Assume that the holes are generated and accelerated toward one of theelectrodes of the EEPROM. Resulting secondary electrons are sufficientlyenergetic to penetrate gate oxide over the substrate and become injectedinto a conductive floating gate. For very small EEPROMs, the floatinggate becomes charged by band-to-band tunneling, a situation whicheliminates the need for a control gate over the floating gate.

U.S. Pat. No. 5,126,967 and U.S. Pat. No. 4,890,259 to R. Sinks describea memory array made of non-volatile transistors that can store analogwaveforms.

The ability of EEPROM transistors to directly record analog waveforms,without A-to-D conversion, gives rise to new applications, such as usein neural networks. This has been pointed out in U.S. Pat. No. 6,125,053where C. Dioris and C. Mead describe use of EEPROMs storing variableamounts of charge generated by impact ionization to represent an analogvalue. This is in contrast to a conventional EEPROM where a floatinggate either stores charge or does not store charge, thereby indicating adigital value. In the '053 patent, an EEPROM is described that permitssimultaneous writing and reading.

An analogous problem is simultaneous programming and erasing operationsin an array. An object of the invention was to devise a memory arraythat has simultaneous programming of one memory region and erasing ofanother memory region.

SUMMARY OF THE INVENTION

The above object has been met with semiconductor non-volatile memoryarray having cells in one row that can be written while cells in anotherrow are erased. The cells feature a non-volatile memory transistor ofthe type having a floating gate, plus a charge injector formed in anisolated but adjacent isolation area, plus customary row and columnaddress lines. The charge injector creates space charge flowing towardthe bottom of the substrate below isolation regions. Because ofproximity of the injector to the memory transistor, one or more of theelectrodes of the memory transistor is biased to attract charge, e.g.holes. Impacts of the holes upon the charged electrode or electrodesgives rise to secondary particles, specifically electrons, by impactionization, having sufficient energy for injecting onto the floatinggate. Current stimulation in the injector, a fast diode, and electrodebias in the transistor, in a carefully controlled manner leads toplacement of precise amounts of charge on the floating gate. A currentmeter placed at an electrode may or could measure the transferred chargeover a particular range, out of several possible ranges, determined bysubstrate and injector region doping. Different doping levels give riseto different conduction thresholds for memory cells in the transistorand hence different ranges. The different thresholds in a transistorarray allow an array to act over an extended range of analog signaltrimming, without analog-to-digital conversion.

To achieve simultaneous writing and erasing, a row being currentlywritten is selected by a word line, while the same line erases anadjacent, non-current row. The word line is spaced by dielectricmaterial from a plurality of polysilicon plates, the spacing creating acapacitive relation relative to the word line. The poly plates havetangs that form control gates of transistors. Tangs extending in onedirection form EEPROM control gates for writing in one row while tangsextending in another direction form control gates for erasing in anotherrow.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram of a portion of a non-volatile transistormemory array in accordance with the present invention.

FIG. 2 is a redrawn schematic drawing of a memory cell shown in thememory array of FIG. 1.

FIG. 3 is a sectional view of a memory cell in the memory array of FIG.1, taken along lines 3-3 of FIG. 4.

FIG. 4 is a top view of a chip layout of a memory cell shown in FIG. 2.

FIG. 5 is a plot of injector current versus voltage in a band-to-bandtunneling operating area contrasted with an avalanche breakdown area fora transistor memory cell of the kind shown in FIG. 2.

FIG. 6 is a plot of injector current as a function of drain and controlgate voltage bias for a transistor memory cell of the kind shown in FIG.2.

FIG. 7 is a plot of number of electrons stored as a function ofthreshold voltage for memory cells of the kind shown in FIG. 2.

FIG. 8 is a sectional view of a word line in a memory cell in the memoryarray of FIG. 1, taken along lines 8-8 of FIG. 4.

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIG. 1, a first memory cell 15 of a non-volatiletransistor memory array has first and second programming lines 11 and13, associated with respective contacts 22 and 26, as well as bit lines17 and 37 and word line 19 all running through the cell and intoneighboring cells. In particular, programming lines 11 and 13, bit line17 and word line 19 run into neighboring cell 115 in a first direction,while bit line 37 runs into neighboring cell 215 in a second direction.Word line 19 is in a capacitive relation to a polysilicon plate, formingcapacitive device 25. Word line 119 similarly relates to anotherpolysilicon plate (130, shown in FIG. 2) forming capacitive device 125.Each memory cell has an EEPROM memory transistor 23 and a currentinjector including a fast diode 29, with a cathode connected to anelectrical contact 22 and to an electrode of an MOS injector transistor21. The injector transistor 21 has a single poly control gate(represented by 21A, 21B), described below. MOS injector transistor 21is biased by either actuation line 36 (21A), or by means of capacitivecoupling via word line 19 (21B), or both, depending on the mode ofoperation. The anode of diode 29 is connected to the transistorsubstrate and electrical contact 24. Biasing of first program line 11 oftransistor 21 provides reverse bias to diode 29. Such reverse biasgenerates current toward the depth of the substrate.

Program lines 11 and 13 are arranged to provide bias to MOS transistor21 when appropriate bias is established on actuation line 33 by ann-channel MOS transistor 35 connected as a plate capacitor. EEPROMmemory transistor 23 has a distributed floating gate formed by the gatesof transistors 35, and 21, essentially lead wire forming line 36, whilethe control gate is a novel capacitively coupled structure partly formedby word line 19.

Word line 19 is shown to be part of a capacitive device 25 in cell 15,as well as capacitive device 125 in a neighboring cell. A feature of theword line and associated capacitive devices is that bias is provided toone cell for writing but in the neighboring cell for erasing in a mannerbut explained below with reference to FIGS. 3 and 4. The word line isone plate of the capacitive devices and may be either above or below theother plates. The other plates are polysilicon structures, one plateassociated with two adjoining memory cells, having tangs or featuresthat form part of an EEPROM akin to a control electrode, as explainedmore fully below.

A current meter 39 associated with bit line 37 and contact 32, measurescurrent through memory transistor 23 via device 25 when transistor 23 isread or written to by placing appropriate bias on bit lines andprogramming lines. The programming lines 11 and 13 are normally floatingduring other times. The bit lines 17 and 37 are biased to provide anaccurate current flow measurement through transistor 23 of a selectedcell. Not shown in FIG. 1 are row and column address circuitry.

A column-wise adjacent cell 115 has the same components as cell 15,namely an MOS transistor 135 connected as a plate capacitor, a currentinjector formed by a diode 129 and injector transistor 121, an EEPROMmemory transistor 123 and a capacitive device 125. A current meter 139reads the output of memory transistor 123 along bit line 137.Programming lines 11 and 13 bias the current injector for conductionwhen appropriate bias is established by actuation line 133, withelectrons driven to the floating gate of memory transistor 123. Themethod of charge injection into the oxide and floating gate or from thefloating gate into the oxide and substrate can be any of the followingmechanisms: photo-emission, Fowler-Nordheim tunneling, hot electroninjection at appropriate temperatures (i.e. not lower than 500° C.), orZener or Avalanche breakdown (i.e. if carriers in substrate acquireenergies in excess of the electron or hole barrier height). Other cellsin the memory array, such as cells 215 and 315 have similar componentsas memory cells 15 and 115, respectively.

The current to or from a selected memory transistor could be measuredduring a programming operation, i.e. channel conductivity present, inorder to have an indication of the amount of stored charge on thefloating gate structure formed by the three gates of transistors 35, 21,and 23. Part of the channel conductivity for MOS transistor 21 isprovided by the injector, in particular, injector diode 29, as seenbelow. Impact ionization is most frequently measured by monitoringsubstrate current in the memory transistor. The source and drain ofmemory transistor 23 are electrically floating at bit line 17 and wordline 19 during programming. Current meter 39 has contact via 32 forreading the state of charge.

To enable low voltage impact ionization, both sides of the injectordiode junction 29 are heavily doped and the barrier thickness isapproximately equal to the depletion width. As an example, thisdimension is 100 Å with a doping level on the lightly doped side of thejunction exceeding 10¹⁷ cm⁻³.

In the memory cell 15 of FIG. 2, two programming lines 11 and 13 controloperation of injector transistor 21 that can reverse bias diode 29.Recalling that this reverse bias of diode 29 generates impact ionizationcurrent that stores charge in the floating gate of memory transistor 23.But memory transistor 23 was said to have a device 25 in a capacitiverelation with respect to word line 19. The device 25 has a polysiliconplate 30 having a first finger or tang 86′ that serves as control gateof memory transistor 23 actuated by word line 19. The word line 19 maybe over or under plate 30, separated by an insulative layer, such asoxide. In the case of being under plate 30, the word line 19 may be aburied word line in an n-well diffusion in order to save space. Anothertang 186 extends out of memory cell 15 to an adjacent injectortransistor as a control gate for the injector. Voltage on the word line19 is capacitively coupled to plate 30 thereby providing voltage forerasing EEPROM memory transistor 23. Simultaneously, the plate providesa voltage to a control gate of an injector transistor in an adjacentcell. In other words, each injector transistor has a control gate thatis a tang of a polysilicon plate, such as plate 30. In the case ofinjector transistor 21, tang 76′ projecting from polysilicon plate 130provides voltage via capacitive coupling with word line 119. Recall thatvoltage bias on line 33 charges line 36, stimulating impact ionizationfrom diode 29 that passes through a common substrate toward memorytransistor 23. Since line 36 serves as floating gate for the memorytransistor, the floating gate remains charged, even after bias isremoved from line 31. The role of tang 76′ is to augment voltage appliedto the control gate of transistor 21 and to allow word line control ofprogramming. In the latter mode of operation, an entire row (or column)of memory cells could be programmed or erased under word line control.In the former mode of operation, some of the voltage for programming orerasing is coupled through a word line, but another part of the neededvoltage is supplied by a voltage applied on line 33, thereby allowingprogramming and erase control of individual cells. The circuit topologyof FIG. 2 is closer to an actual layout of a cell, compared to FIG. 1,because word lines are at right angles to bit lines.

With reference to FIG. 3, a p-type wafer substrate 61 is seen to havep-wells 63, 65, and 67 separated by insulative regions 73, 75, 77, and79 formed by trench isolation. The p-wells have n+ doped implants 62 and64 upon which are built the conductive vias 72 and 74. The implants 62and 64 define source and drain electrodes for an MOS transistor 21having a poly gate 76. The transistor 21 is connected to the fast diode29 in FIGS. 1 and 2. Here the fast diode is seen to be formed byp-implanted region 81 abutting n+ region 62.

Together, transistor 21 and the fast diode form a current injector. Asthe reverse voltage across the diode is increased, the leakage currentremains essentially constant until the breakdown voltage is reachedwhere the current increases dramatically. This breakdown voltage is theZener voltage. While for the conventional rectifier or diode it isimperative to operate below this voltage, the current injector diode isintended to operate at the Zener voltage.

The following is the correspondence between elements of FIGS. 1 and 2and features shown in FIG. 3. Vias 72 and 74 of FIG. 3 terminate incontacts 22 and 26 of FIGS. 1 and 2. Diode 29 of FIGS. 1 and 2 is formedp-n junction 62 and 81 of FIG. 3. Subsurface N region 62 is connected byvia 72 in FIG. 3 to program line 11 at contact 22 in FIGS. 1 and 2.Subsurface p region 64 is connected by via 74 in FIG. 3 to bit line 13at contact 26 in FIGS. 1 and 2. Subsurface region 91 contacted by via 90is the actuation line 33 for bias of the first memory cell 15 in FIG. 1.Control poly gate 76 is joined to control poly gate 86 by a line,represented by line 85 in FIG. 3 and the connected gates of transistors21 and 23 in FIGS. 1 and 2. Control poly gate 76 is tang 76′ of polyplate 130 in FIG. 2 that may be controlled by voltages applied to wordline 119. The same gate is also controlled by voltage applied on line 33of MOS device 35 for biasing of the gate to establish writing orprogramming in transistor 23. With word line control, a block of memorytransistors may be programmed at the same time. With gate control fromdevice 33, a single transistor is programmed.

In FIG. 3, the via 97 communicates with current meter 39, seen in FIGS.1 and 2, through contact 32. Memory transistor 23 has a control polygate 86 spaced between drain 82 and source 84, in turn communicatingthrough vias 97 and 99 to the drain 82 and the source 84. Subsurfaceregion 93 connected by via 94 for external contact is actuation line 133for bias of the second memory cell 115 in FIG. 1. Recall that transistor23 has a floating gate formed three gate leads for transistors 35, 21,and 22 seen in FIGS. 1 and 2. The gate leads are represented by dashedline 85 in FIG. 3. Control gate 86 is a tang 86N of poly plate 30 ofdevice 25 seen in FIG. 2. Contact 32 is associated with current meter 39on line 37. Each well may have a current meter although only the currentmeter 39 associated with measuring charge on a memory cell is discussedherein.

In FIG. 3, the transistor 223 is a memory transistor of an adjacentcell. The transistor 223 is symmetric with transistor 23 having a sharedelectrode 84 and drain electrode 88. Via 101 connects drain electrode 88to a drain contact. The via 99 above shared electrode 84 forms a planeof symmetry except for current measuring electrodes and provides biasfor associated transistors 23 and 223, similar to via 90 and subsurfaceregion 91, but using actuation line 103 seen in FIG. 4. Control polyregion 92 is a tang of another poly plate and so is poly region 176 ofinjection transistor 221. The floating gate for memory transistor 223 isactually formed by three gate leads, analogous to the leads oftransistors 35, 21, and 23, indicated by dashed line 185. To the rightof p-well 65 is p-well 67, separated by isolation region 77. The dopedn-implants 162 and 164 are in p-well 67, below conductive vias 172 and174. The implants 162 and 164 define electrodes for MOS injectiontransistor 221. A cooperating part of the current injector is formed bya diode having p-implanted region 181 abutting n+ region 162. The diodeis made by implants at the same time and in the same manner as the diodeassociated with transistor 21. The diode is controlled by transistor221, having control gate 176, operating in the same manner as transistor21. Electrons for charge storage on floating gates 85 and 185 aregenerated by this impact ionization. These electrons are involved intransfer to the floating gates by tunneling hot electron injection orother known mechanisms.

The measured current on current meter 39 is proportional to storedcharge on the floating gate of the memory transistors in the same well.Since more than one memory transistor can share the same well,calibration is needed to relate measured current to stored charge. Oneof the remarkable features of the present invention is illustrated inFIG. 4. The word line 19 is seen to lie under or over poly plate 30. Thepoly plate 30 has a pair of tangs 86′ and 186, extending in oppositedirections. The tang 86′ is the control gate 86 of memory transistor 23.See FIG. 3. The tang 186 is the control gate of an injector transistorin another row. Voltage on word line 19 induces voltage on poly plate30, a capacitor-like device. Tang 86′ causes erasing of memory cell 23while tang 186 initiates impact ionization current in an injectortransistor in another row and hence writing in another row. This issimilar to action by poly plate 130, spaced over or under word line 119by an insulative layer, such as oxide, and having tang 76 projectinginto injector transistor 21 as its control gate. Voltage on word line119 induces voltage on poly plate 130 and hence on tang 76. This voltageinitiates impact ionization current that stores charge in the floatinggate of memory transistor 23. Via 99, a common electrode for memorytransistor 23 and 223 in FIG. 3, is an axis of symmetry for structuresto the right, except for current measuring lines. Lateral symmetryallows two memory transistors to share the same well and achieve a gooddegree of compactness.

Each word line has a capacitive relation with a plurality of polyplates, all spaced apart from the word line by insulative material, suchas oxide. A voltage applied to a word line can cause writing to allnon-volatile memory transistors in one row and erasing to allnon-volatile memory transistors in another row. Each poly platepreferably has two tangs extending in opposite directions, forming polygates of transistors in adjacent rows.

In FIG. 5, the substrate current is plotted against voltage of the gateelectrode of the MOS transistor associated with the injector. Note thatabove 1.0 volts, at region 200, there is an almost linear increase incurrent as voltage increases. To the left of the vertical line “L” isthe band-to-band tunneling region. To the right of the vertical line Lis the avalanche region. In the avalanche region, there is no longer alinear increase in current as voltage increases. The avalanche regionshould be avoided. The characteristic curve of FIG. 3 is for aparticular level of injector doping. Different curves exist fordifferent dopings.

In FIG. 6, different characteristic curves are shown relating slightlydifferent substrate current, plotted along the vertical axis, fordifferent control gate relative to drain bias voltages, plotted on thehorizontal axis. Five storage levels are shown.

In FIG. 7, it is seen that different threshold voltages, permitdifferent ranges of stored electrons to be selected. The first pair ofcurves 201, 203 corresponds to stored electrons from first substratecurrent at a first threshold voltage. The second pair of curves 205, 207corresponds to stored electrons from a second substrate current for asecond threshold voltage. A similar situation exists for the third pairof curves 211, 213 and the fourth pair of curves 215, 217. So differentthreshold voltages for the storage transistors can select varyingamounts of stored charge. Differing threshold voltages could beassociated with different rows in a memory array.

In FIG. 8, word line 19 is shown an example of diffused p+ layer inn-well 140 between isolation regions 132 and 134. The n-well 119 isformed in the p-type substrate 136. By diffusing the word line in thesubstrate, the word line geometry is made more compact. A layer of oxide138 is deposited to a thickness of at least 1500 Å before the poly plate43 is deposited. Poly plate 43 has the usual thickness of a controlgate, perhaps 3000 Å. The diffused word line 19 runs under a pluralityof poly plates, for example, all of the poly plates in a row. Whetherthe poly plates are diffused under the word line or not, all of the polyplates associated with one type of control gate in a row of memory cellsare aligned under or over the word line in parallel relation therewith.

Word line 19 behaves as one plate of a capacitor. The layer of oxide 138acts a dielectric separator for a second capacitor plate, the poly plate43. In a memory array, the buried word line and the plurality of polyplates form a new type of semiconductor device in a memory array.

Burying of the word line is optional. The word line could be plated overthe poly plates. However, by burying the word line a much more compactmemory array is formed. As usual, each word line is controlledindependently. Typically, each word line controls a single row or columnof a memory array for a write operation and a single row or column foran erase operation. Tangs extending from each poly plate form controlgates for transistors as explained above. Because the tangs extend fromthe poly plates in opposite directions it is possible to control writingin one row where the tangs operate or control injector transistors andto control erasing in another row where the tangs operate or control amemory transistor.

In operation, following are suggested voltages for word lines and bitlines for memory cell programming where the cell is an array having “M’rows, where “M” is greater than “i”. WL_(i) is the “i”th word line where“i” is an integer and BL_(i) is the “i”th bit line. The n-well is atapproximately positive 5 volts and the p-substrate is grounded. Thevalues below are sub-bandgap ionization voltages. Program Cell WL_(i) −1 = GND BL_(i) − 1 = ˜+3-5 v WL_(i) = ˜+5 v BL_(i) = FLOAT WL_(i) + 1 =GND BL_(i) + 1 = FLOAT

Following are suggested voltages for erasing, assume a Fowler-Nordheimerase mode. The n-well is at approximately negative 15 volts and thep-substrate is grounded. Erase Row WL_(i) − 1 = GND BL_(i) − 1 = FLOATWL_(i) = ˜−15 v BL_(i) = FLOAT WL_(i) + 1 = GND BL_(i) + 1 = FLOAT

Erase Block WL_(i) − 1 = ˜−15 v BL − FLOAT (ALL) WL_(i) = ˜−15 vWL_(i) + 1 = ˜−15 v

Following are suggested read voltages. The n-well and the p-substrateare both grounded. The active bit line voltage must be lower than theprogramming voltage. Read Cell WL_(i) − 1 = GND BL_(i) − 1 = FLOATWL_(i) = ˜+5 v BL_(i) = +V_(DD) (˜1.8 v)+ WL_(i) + 1 BL_(i) + 1 = FLOATThe above voltage values are exemplary and intended to indicate relativevalues. Actual values will differ.

1. A non-volatile memory array having a plurality of memory cells inrows and columns, each memory cell comprising, a non-volatile memorytransistor with a source, drain, and channel disposed within a firstisolation region in the substrate; an injector transistor having asource and drain disposed within a second isolation region in thesubstrate with a space charge means for accelerating charge carriers toat least one of the source and drain, and a word line portion incapacitive plate relation to serve as a control gate for the memorytransistor.
 2. The apparatus of claim 1 wherein rows of the array haveword lines and columns have bit and program lines, all with selectivelyapplied bias voltages, the word lines and poly plates of adjacent rowsconnected in a manner whereby memory cells in a first row can beselectively written to, simultaneously erasing of memory cells in anadjacent row.
 3. The apparatus of claim 1 wherein different rows of thememory array have different doping densities, thereby establishingdifferent threshold voltages in different rows.
 4. The apparatus ofclaim 1 wherein memory transistors of common thresholds may be disposedin a row, with different rows having different thresholds.
 5. Theapparatus of claim 4 wherein different rows of memory transistors span arange of thresholds.
 6. The apparatus of claim 1 wherein each memorycell is associated with an electrically communicating current metermeasuring stored charge in the memory cell.
 7. The apparatus of claim 1wherein each memory cell has at least two mutually connected floatinggate transistors.
 8. The apparatus of claim 1 wherein the memory arraycomprises a plurality of capacitive plates of polysilicon.
 9. Theapparatus of claim 1 wherein the capacitive plate has a first regionforming said control gate and a second region that forms a control meansfor an injector transistor in an adjacent row to the memory cell. 10.The apparatus of claim 9 wherein the injector transistor in the adjacentrow is in an adjacent column to the memory cell.
 11. The apparatus ofclaim 1 wherein the space charge means is a p-n junction having thesource of the injector transistor as a member of the junction.
 12. Theapparatus of claim 1 wherein the charge injector diode is a p-n junctionhaving the drain of the injector transistor as a member of the junction.13. A non-volatile memory array comprising, a plurality of memory cellsin rows and columns, each cell having a non-volatile memory transistorwith a source, drain, and channel and an auxiliary transistor means forgenerating space charge for programming the non-volatile memorytransistor; and a word line in capacitive relation to a first row ofmemory cells of the array via a plurality of capacitive plates, each ofthe plurality of capacitive plates comprising a first region of the wordline forming a control gate for a memory transistor.
 14. Thenon-volatile memory array of claim 13 wherein the each of the pluralityof capacitive plates further comprises a second region forming a controlgate for a programming transistor in a second row of memory cells of thearray.
 15. The non-volatile memory array of claim 13 wherein thenon-volatile memory transistors are disposed within a first isolationregion within the substrate and the auxiliary transistors are disposedwithin a second isolation region within the substrate.
 16. Thenon-volatile memory array of claim 13 wherein the programmingtransistors are configured to transfer charge carriers to the capacitiveplate by means of avalanche injection.
 17. The non-volatile memory arrayof claim 13 wherein the means for generating space charge comprises acharge injector communicating charge to at least one of the source anddrain of the auxiliary transistor, the accelerated charge carriersgiving rise to energetic charged particles which can be stored in a gateof a non-volatile memory transistor.
 18. A non-volatile memory arrayhaving a plurality of memory cells in rows and columns comprising: anon-volatile memory transistor in each cell with a source, drain, andchannel; an injector transistor associated with each cell having meansfor generating space charge for use with an associated non-volatilememory transistor, and a plurality of word lines, each word line havinga plurality of capacitive plates, each of the plurality of capacitiveplates having a first region forming a control gate for a memorytransistor in one row and a second region forming a control gate for aninjector transistor in another row.